Modern CPU Microarchitecture, RTL Design, and Verification: My Journey Across ARM and x86 Platforms

In this presentation, I will walk through my professional journey as a CPU designer and verification engineer, highlighting my experience in ARM-based Snapdragon-X CPUs and x86-based microarchitecture work at Intel. I will discuss the practical challenges of RTL design, integer execution pipelines, microarchitecture specifications, clocking methodologies, timing closure, and low-power optimization. Through real project examples — from pipeline design, SoC feature implementation, verification strategies, and energy-efficient IP development — I aim to provide a clear understanding of how modern CPU blocks are conceived, architected, implemented, and validated. This presentation combines industry-level CPU design principles with hands-on learning from multiple silicon development cycles.
Who is this presentation for?
This presentation is intended for: • Students and early-career engineers interested in CPU design or verification • Professionals transitioning into microarchitecture or RTL development • Hardware engineers curious about ARM and x86 CPU pipeline design • Anyone who wants real-world insight into the semiconductor design workflow
Prerequisite knowledge:
To understand the presentation smoothly, the audience should ideally know: • Basics of digital logic design (combinational and sequential circuits) • Fundamentals of computer architecture (pipelines, hazards, caches) • High-level understanding of RTL (Verilog/VHDL) concepts • General semiconductor design flow (front-end to STA/PnR) • Basic familiarity with verification principles
What you'll learn?
By the end of the presentation, the audience will learn: • How modern ARM and x86 CPU execution pipelines are designed • What microarchitects consider when defining RTL features • How timing closure, logic depth reduction, and area trade-offs guide design decisions • How SoC clocking, cluster ownership, and power optimization are handled • How verification teams ensure coverage, catch bugs, and validate complex features • How research work such as Minimum Energy Point optimization shapes low-power IP • How large semiconductor companies execute end-to-end CPU development

I am a front-end CPU designer specializing in ARM architecture, currently contributing to the development of Snapdragon-X series CPUs. I hold a Master’s degree in Computer Engineering from Texas A&M University with a perfect 4.0 GPA and a Bachelor’s degree in Electronics and Communication Engineering from BMS College of Engineering with a CGPA of 9.41/10. Throughout my career, I have worked extensively in CPU design, micro-architecture, RTL development, verification, SoC design, and energy-efficient hardware research across Qualcomm, Intel, and IBM. I have hands-on experience in ARM SPE/GCS, integer execution pipelines, timing closure, coverage-driven verification, spec definition, and clocking methodologies.